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publication number S70FL256P_00 revision 04 issue date june 24, 2011 S70FL256P S70FL256P cover sheet 256-mbit cmos 3.0 volt flash memory with 104-mhz spi (serial peripher al interface) multi i/o bus data sheet notice to readers: this document states the current techni cal specifications regarding the spansion product(s) described herein. each product described herein may be designated as advance information, preliminary, or full production. see notice on data sheet designations for definitions.
2 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet notice on data sheet designations spansion inc. issues data sheets with advance informat ion or preliminary designati ons to advise readers of product information or intended s pecifications throughout the produc t life cycle, including development, qualification, initial production, and full production. in all cases, however, reader s are encouraged to verify that they have the latest information before finalizi ng their design. the following descriptions of spansion data sheet designations are presented here to hi ghlight their presenc e and definitions. advance information the advance information designation i ndicates that spansion inc. is de veloping one or more specific products, but has not committed any des ign to production. information pr esented in a document with this designation is likely to change, and in some cases, development on the product may discontinue. spansion inc. therefore plac es the following conditions upo n advance information content: ?this document contains information on one or more products under development at spansion inc. the information is intended to help you evaluate this product. do not design in this product without contacting the factory. spansion inc. reserves the right to change or discontinue work on this proposed product without notice.? preliminary the preliminary designation indicates that the product development has pr ogressed such that a commitment to production has taken place. this designation covers several aspects of the product life cycle, including product qualification, initial production, and the subsequent phases in the manufacturing process that occur before full production is achieved. changes to the technical specifications presented in a preliminary document should be expected while keeping these aspects of production under c onsideration. spansion places the following conditi ons upon preliminary content: ?this document states the current technical specifications regarding the spansion product(s) described herein. the preliminary status of this document indicates that product qualification has been completed, and that initial production has begun. due to the phases of the manufacturing process that require maintaining efficiency and quality, this document may be revised by subsequent versions or modifications due to changes in technical specifications.? combination some data sheets contain a combination of products with different designati ons (advance information, preliminary, or full production). th is type of document distinguishes t hese products and their designations wherever necessary, typically on the first page, th e ordering information page, and pages with the dc characteristics table and the ac er ase and program table (in the table notes). the disclaimer on the first page refers the reader to the notice on this page. full production (no designation on document) when a product has been in production for a period of ti me such that no changes or only nominal changes are expected, the preliminary desi gnation is removed from the data sheet. nominal changes may include those affecting the number of ordering part numbers available, such as the a ddition or deletion of a speed option, temperat ure range, package type, or v io range. changes may also include those needed to clarify a description or to correct a typographic al error or incorrect specificati on. spansion inc. applies the following conditions to documents in this category: ?this document states the current technical specifications regarding the spansion product(s) described herein. spansion inc. deems the products to have been in sufficient production volume such that subsequent versions of this document are not expected to change. however, typographical or specification corrections, or modifications to the valid combinations offered may occur.? questions regarding these document designations may be directed to your local sales office.
publication number S70FL256P_00 revision 04 issue date june 24, 2011 distinctive characteristics architectural advantages ? single power supply operation ? full voltage range: 2.7 to 3.6v read and write operations ? memory architecture ? uniform 64 kb sectors ? top or bottom parameter block (two 64-kb sectors broken down into sixteen 4-kb sub-sectors each) for each flash die ? uniform 256 kb sectors (no 4-kb sub-sectors) ? 256-byte page size ? program ? page program (up to 256 bytes) in 1.5 ms (typical) ? program operations are on a page by page basis ? accelerated programming mode via 9v w#/acc pin ? quad page programming ? erase ? bulk erase function for each flash die ? sector erase (se) command (d8h) for 64 kb and 256 kb sectors ? sub-sector erase (p4e) command (20h) for 4 kb sectors (for uniform 64-kb sector device only) ? sub-sector erase (p8e) command (40h) for 8 kb sectors (for uniform 64-kb sector device only) ? cycling endurance ? 100,000 cycles per sector typical ? data retention ? 20 years typical ? device id ? jedec standard two-byte electronic signature ? res command one-byte electronic signature for backward compatibility ? one time programmable (otp) area on each flash die for permanent, secure identification; can be programmed and locked at the factory or by the customer ? cfi (common flash interface) compliant: allows host system to identify and accommodate multiple flash devices ? process technology ? manufactured on 0.09 m mirrorbit ? process technology ? package option ? industry standard pinouts ? 16-pin so package (300 mils) ? 24-ball bga (6 x 8 mm) package, 5 x 5 pin configuration performance characteristics ? speed ? normal read (seria l): 40 mhz clock rate ? fast_read (serial): 104 mhz clock rate (maximum) ? dual i/o fast_read: 80 mhz clock rate or 20 mb/s effective data rate ? quad i/o fast_read: 80 mhz clock rate or 40 mb/s effective data rate ? power saving standby mode ? standby mode 160 a (typical) ? deep power-down mode 6 a (typical) memory protection features ? memory protection ? w#/acc pin works in conjunction with status register bits to protect specified memory areas ? status register block protection bits (bp2, bp1, bp0) in status general description this document contains information for th e S70FL256P device, which is a dual die stack of two s25fl129p die. for detailed specifications, please refer to the discrete die data sheet: S70FL256P 256-mbit cmos 3.0 volt flash memory with 104-mhz spi (serial peripher al interface) multi i/o bus data sheet document publication identification number (pid) s25fl129p data s heet s25fl129p_00
4 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet table of contents distinctive characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2. connection diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3. input/output descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4. logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5. ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 5.1 valid combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6. device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.1 programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2 simultaneous die operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.3 sequential reads. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 sector/bulk erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.5 status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.6 configuration register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.7 block protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 7. read identification (rdid) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9. test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10. ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 10.1 capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 11. physical dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 11.1 sl3 016 ? 16-pin wide plastic small outline package (300-mil body width) . . . . . . . . . . . 16 11.2 zsa024 ? 24-ball ball grid array (6 x 8 mm) package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 12. revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
june 24, 2011 S70FL256P_00_04 S70FL256P 5 data sheet figures figure 2.1 16-pin plastic small outline package (so) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 2.2 6 x 8 mm 24-ball bga pa ckage, 5 x 5 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 9.1 ac measurements i/o waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 10.1 ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet tables table 5.1 S70FL256P valid combinations table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 7.1 product group cfi device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 table 8.1 dc characteristics (cmos compatible) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 9.1 test specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
june 24, 2011 S70FL256P_00_04 S70FL256P 7 data sheet 1. block diagram s i/io0 s i/io0 w#/acc/io2 w#/acc/io2 s o/io1 hold#/io 3 hold#/io 3 v ss v ss s ck s ck c s #1 c s # vcc vcc s i/io0 w#/acc/io2 hold#/io 3 v ss s ck c s #2 c s # vcc s o/io1 s o/io1 fl129p fl as h memory fl129p fl as h memory
8 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet 2. connection diagrams figure 2.1 16-pin plastic small outline package (so) note: dnc = do not connect (reserved for future use) figure 2.2 6 x 8 mm 24-ball bga package, 5 x 5 pin configuration 1 2 3 4 16 15 14 1 3 hold#/io 3 vcc dnc dnc dnc dnc s i/io0 s ck 5 6 7 8 12 11 10 9 w#/acc/io2 gnd dnc dnc dnc c s 2# c s 1# s o/io1 3 25 4 1 dnc dnc dnc dnc b d e a c gnd sck dnc vcc dnc cs2# cs1# dnc w#/acc/io2 dnc si/io0 so/io1 dnc hold#/io3 dnc dnc dnc dnc dnc dnc
june 24, 2011 S70FL256P_00_04 S70FL256P 9 data sheet 3. input/output descriptions 4. logic symbol signal i/o description so/io1 i/o serial data output : transfers data serially out of the device on the falling edge of sck. functions as an i/o pin in dual and quad i/o, and quad page program modes. si/io0 i/o serial data input : transfers data serially into the device. device latches commands, addresses, and program data on si on the rising edge of sck. functions as an i/o pin in dual and quad i/o mode. sck input serial clock : provides serial interface timing. latches commands, addresses, and data on si on rising edge of sck. triggers output on so after the falling edge of sck. cs1# cs2# input chip selects : places one of the flash die in active power mode when driven low. deselects flash die and places so at high impedance when high. after power-up, device requires a falling edge on cs1# and cs2# before any command is written. device is in standby mode when a program, erase, or write status register operation is not in progress. hold#/io3 i/o hold : pauses any serial communication with the device without deselecting it. when driven low, so is at high impedance, and all input at si and sck are ignored. requires that cs1# or cs2# also be driven low. functions as an i/o pin in quad i/o mode. w#/acc/io2 i/o write protect : protects the memory area specified by status register bits bp2:bp0. when driven low, prevents any program or erase command from altering the data in the protected memory area. functions as an i/o pin in quad i/o mode. v cc input supply voltage gnd input ground c s 1# s o/io1 w#/acc/io2 gnd s i/io0 s ck hold#/io 3 v cc c s 2#
10 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet 5. ordering information the ordering part number is formed by a valid combination of the following: 5.1 valid combinations table 5.1 lists the valid combinations co nfigurations planned to be support ed in volume for this device. note: 1. package marking omits the leading ?s70? and speed, package and model number. s70fl 256 p 0x m f i 00 1 packing type (note 1) 0 = tray 1 = tube 3 = 13? tape and reel model number (additional ordering options) 21 = bga package, uniform 256 kb sectors 20 = bga package, uniform 64 kb sectors 01 = so package, uniform 256 kb sectors 00 = so package, uniform 64 kb sectors temperature range i = industrial (?40c to + 85c) package materials f = lead (pb)-free h = low-halogen, lead (pb)-free package type m = 16-pin so package b = 24-ball bga 6 x 8 mm package, 1.00 mm pitch speed 0x = 104 mhz device technology p = 0.09 m mirrorbit ? process technology density 256 = 256 mbit device family s70fl spansion stacked memory 3.0 volt-only, serial peripheral interface (spi) flash memory table 5.1 S70FL256P valid combinations table S70FL256P valid combinations package marking base ordering part number speed option package and temperature model number packing type S70FL256P 0x mfi 00 0, 1, 3 70fl256p0xmfi00 01 70fl256p0xmfi01 bhi 20 0, 3 70fl256p0xbhi20 21 70fl256p0xbhi21
june 24, 2011 S70FL256P_00_04 S70FL256P 11 data sheet 6. device operations 6.1 programming each flash die must be programmed independently due to the nature of the dual die stack. 6.2 simultaneous die operation the user may only access one flash di e of the dual die stack at a time via its respective chip select. 6.3 sequential reads sequential reads are not supported across the end of t he first flash die to the begi nning of the second. if the user desires to sequentially read across the two die, data must be read out of the first die via cs1# and then read out of the second die via cs2#. 6.4 sector/bulk erase a sector erase command must be issued for sectors in each flash die separately. fu ll device bulk erase via a single command is not supported due to the nature of the dual die stack. a bulk erase command must be issued for each die. 6.5 status register each flash die of the dual die sta ck is managed by its own status regist er. reads and updates to the status registers must be managed s eparately. it is recommended that status register control bit settings of each die are kept identical to maintain c onsistency when switching between die. 6.6 configuration register each flash die of the dual die stack is managed by its own configuration r egister. updates to the configuration register control bits must be managed separately. it is reco mmended that configuration register control bi t settings of each die are ke pt identical to maintain consistency when switching between die. 6.7 block protection each flash die of the dual die stack will maintain its own block protection. updates to the tbprot and bpnv bits of each die must be manage d separately. by default, each di e is configured to be protected starting at the top (highest address) of each arra y, but no address range is protected. it is recommended that the block protection settings of each die are kept identical to maintain consistency when switching between die. 7. read identification (rdid) the read identification (rdid) comma nd outputs the one-byte manufacturer identification, followed by the two-byte device identification and t he bytes for the common flash interface (cfi) tables. each die of the fl256p dual die stack will have identical identification data as the fl129p die, with the exception of the cfi data at byte 27h, as shown in table 7.1 . table 7.1 product group cfi device geometry definition byte data description 27h 19h device size = 2^n byte
12 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet 8. dc characteristics this section summarizes the dc characteristics of t he device. designers should check that the operating conditions in their circuit match the measurement c onditions specified in the test specifications in table 9.1 on page 13 , when relying on the quoted parameters. notes: 1. typical values are at t ai = 25c and v cc = 3v. 2. bulk erase is on a die per die basis, not for the whole device. table 8.1 dc characteristics (cmos compatible) symbol parameter test conditions limits unit min. typ. (1) max. v cc supply voltage 2.7 3.6 v v hh acc program acceleration voltage v cc = 2.7v to 3.6v 8.5 9.5 v v il input low voltage -0.3 0.3 x v cc v v ih input high voltage 0.7 x v cc v cc +0.5 v v ol output low voltage i ol = 1.6 ma, v cc = v cc min. 0.4 v v oh output high voltage i oh = -0.1 ma v cc -0.6 v i li input leakage current v cc = v cc max, v in = v cc or gnd ? 2a i lo output leakage current v cc = v cc max, v in = v cc or gnd ? 2a i cc1 active power supply current - read (so = open) at 80 mhz (dual or quad) 44 ma at 104 mhz (serial) 32 at 40 mhz (serial) 15 i cc2 active power supply current (page program) cs# = v cc 26 ma i cc3 active power supply current (wrr) cs# = v cc 15 ma i cc4 active power supply current (se) cs# = v cc 26 ma i cc5 active power supply current (be) (2) cs# = v cc 26 ma i sb1 standby current cs# = v cc ; so + v in = gnd or v cc 160 500 a i pd deep power-down current cs# = v cc ; so + v in = gnd or v cc 620 a
june 24, 2011 S70FL256P_00_04 S70FL256P 13 data sheet 9. test conditions figure 9.1 ac measurements i/o waveform note: 1. input rise and fall times are 0-100%. table 9.1 test specifications symbol parameter min max unit c l load capacitance 30 pf input rise and fall times (1) 5ns input pulse voltage 0.2 v cc to 0.8 v cc v input timing reference voltage 0.3 v cc to 0.7 v cc v output timing reference voltage 0.5 v cc v 0. 8 v cc 0.2 v cc 0.7 v cc 0. 3 v cc inp u t level s inp u t a nd o u tp u t timing reference level s 0.5 v cc
14 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet 10. ac characteristics notes: 1. typical program and erase times assume the following conditions: 25c, v cc = 3.0v; 10,000 cycles; checkerboard data pattern. 2. under worst-case conditions of 85c; v cc = 2.7v; 100,000 cycles. 3. acceleration mode (9v acc) only in program mode, not erase. 4. only applicable as a constraint for wrr instruction when srwd is set to a ?1?. 5. t wh + t wl must be less than or equal to 1/f c . 6. ? full vcc range (2.7 ? 3.6v) and cl = 30 pf. 7. ? regulated vcc range (3.0 ? 3.6v) and cl = 30 pf. 8. bulk erase is on a die per die basis, not for the whole device. 9. when switching between die, a minimum time of t cs must be kept between the rising edge of one chip select and the falling edge of the other for operations and data to be valid. figure 10.1 ac characteristics symbol (notes) parameter (notes) min. (notes) typ (notes) max (notes) unit f r sck clock frequency for read command dc 40 mhz sck clock frequency for rdid command dc 50 mhz f c sck clock frequency for all others: fast_read, pp, qpp, p4e, p8e, se, be, dp, res, wren, wrdi, rdsr, wrr, read_id dc 104 (serial) 80 (dual/quad) mhz t wh , t ch (5) clock high time 4.5 ns t wl , t cl (5) clock low time 4.5 ns t crt , t clch clock rise time (slew rate) 0.1 v/ns t cft , t chcl clock fall time (slew rate) 0.1 v/ns t cs (9) cs# high time (read instructions) cs# high time (program/erase) 10 50 ns t css cs# active setup time (relative to sck) 3 ns t csh cs# active hold time (relative to sck) 3 ns t su:dat data in setup time 3 ns t hd:dat data in hold time 2 ns t v clock low to output valid 0 9 (serial) ? 10.5 (dual/quad) ? 7.8 (serial) ? 9 (dual/quad) ? ns t ho output hold time 0 ns t dis output disable time 8ns t hlch hold# active setup time (relative to sck) 3 ns t chhh hold# active hold time (relative to sck) 3 ns t hhch hold# non active setup time (relative to sck) 3 ns t chhl hold# non active hold time (relative to sck) 3 ns t hz hold# enable to output invalid 8 ns t lz hold# disable to output valid 8 ns t wps w#/acc setup time (4) 20 ns t wph w#/acc hold time (4) 100 ns t w wrr cycle time 50 ms t pp page programming (1)(2) 1.5 3 ms t ep page programming (acc = 9v) (1)(2)(3) 1.2 2.4 ms t se sector erase time (64 kb) (1)(2) 0.5 2 sec sector erase time (256 kb) (1)(2) 28sec t be bulk erase time (1)(2)(8) 128 256 sec t pe parameter sector erase time (4 kb or 8 kb) (1)(2) 200 800 ms t res deep power-down to standby mode 30 s t dp time to enter deep power-down mode 10 s t vhh acc voltage rise and fall time 2.2 s t wc acc at v hh and v il or v ih to first command 5 s
june 24, 2011 S70FL256P_00_04 S70FL256P 15 data sheet 10.1 capacitance notes: 1. sampled, not 100% tested. 2. test conditions t a = 25c, f = 1.0 mhz. 3. for more information on pin capacitance, please consult the ibis models. symbol parameter test conditions min max unit c in input capacitance (applies to cs1#, cs2#, sck, si/io0, so/io1, w#/acc/io2, hold#/io3) v out = 0v 6 pf c out output capacitance (applies to si/io0, so/io1, w#/acc/io2, hold#/io3) v in = 0v 8 pf
16 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet 11. physical dimensions 11.1 sl3 016 ? 16-pin wide plastic small outline package (300-mil body width) 3644 \ 16-038.03 rev c \ 02.03.10 (jk) notes: 1. all dimensions are in both inches and millmeters. 2. dimensioning and tolerancing per asme y14.5m - 1994. 3. dimension d does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.15 mm per end. dimension e1 does not include interlead flash or protrusion interlead flash or protrusion shall not exceed 0.25 mm per side. d and e1 dimensions are determined at datum h. 4. the package top may be smaller than the package bottom. dimensions d and e1 are determined at the outmost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs and interlead flash. but including any mismatch between the top and bottom of the plastic body. 5. datums a and b to be determined at datum h. 6. "n" is the maximum number of terminal positions for the specified package length. 7. the dimensions apply to the flat section of the lead between 0.10 to 0.25 mm from the lead tip. 8. dimension "b" does not include dambar protrusion. allowable dambar protrusion shall be 0.10 mm total in excess of the "b" dimension at maximum material condition. the dambar cannot be located on the lower radius of the lead foot. 9. this chamfer feature is optional. if it is not present, then a pin 1 identifier must be located within the index area indicated. 10. lead coplanarity shall be within 0.10 mm as measured from the seating plane. . package sl3016 (inches) sl3016 (mm) jedec ms-013(d)aa ms-013(d)aa symbol min max min max a 0.093 0.104 2.35 2.65 a1 0.004 0.012 0.10 0.30 a2 0.081 0.104 2.05 2.55 b 0.012 0.020 0.31 0.51 b1 0.011 0.019 0.27 0.48 c 0.008 0.013 0.20 0.33 c1 0.008 0.012 0.20 0.30 d 0.406 bsc 10.30 bsc e 0.406 bsc 10.30 bsc e1 0.295 bsc 7.50 bsc e .050 bsc 1.27 bsc l 0.016 0.050 0.40 1.27 l1 .055 ref 1.40 ref l2 .010 bsc 0.25 bsc n 16 16 h 0.10 0.30 0.25 0.75 0 8 0 8 1 5 15 5 15 2 0 0
june 24, 2011 S70FL256P_00_04 S70FL256P 17 data sheet 11.2 zsa024 ? 24-ball ball grid array (6 x 8 mm) package 3645 16-038.86 rev a \ 02.26.10 notes: 1. dimensioning and tolerancing methods per asme y14.5m-1994. 2. all dimensions are in millimeters. 3. ball position designation per jep95, section 4.3, spp-010. 4. e represents the solder ball grid pitch. 5. symbol "md" is the ball matrix size in the "d" direction. symbol "me" is the ball matrix size in the "e" direction. n is the number of populated solder ball positions for matrix size md x me. 6 dimension "b" is measured at the maximum ball diameter in a plane parallel to datum c. datum c is the seating plane and is defined by the crowns of the solder balls. 7 sd and se are measured with respect to datums a and b and define the position of the center solder ball in the outer row. when there is an odd number of solder balls in the outer row sd or se = 0.000. when there is an even number of solder balls in the outer row, sd or se = e/2 8. "+" indicates the theoretical center of depopulated balls. 9 a1 corner to be identified by chamfer, laser or ink mark, metallized mark indentation or other means. package zsa024 jedec n/a d x e 8.00 mm x 6.00 mm package symbol min nom max note a --- --- 1.20 profile a1 0.20 --- --- ball height a2 0.70 --- 0.90 body thickness d 8.00 bsc. body size e 6.00 bsc. body size d1 4.00 bsc. matrix footprint e1 4.00 bsc. matrix footprint md 5 matrix size d direction me 5 matrix size e direction n 24 ball count ? b 0.35 0.40 0.45 ball diameter ee 1.00 bsc. ball pitch ed 1.00 bsc ball pitch sd / se 0.00 solder ball placement a1 depopulated solder balls
18 S70FL256P S70FL256P_00_04 june 24, 2011 data sheet 12. revision history section description revision 01 (march 3, 2010) initial release revision 02 (march 17, 2010) valid combinations corrected package marking specification from discrete to mcp format read identification (rdid) added section to explain cfi change from fl129p revision 03 (june 17, 2010) general changed product description from ?256-mbit cmos 3.0 volt flash memory with 93-mhz spi serial (serial peripheral interface) multi i/o bus? to ?256-mbit cmos 3.0 volt flash memory with 104-mhz spi serial (serial peripheral interface) multi i/o bus? changed data sheet status from advanced information to preliminary distinctive characteristics changed normal read clock rate from 36 to 40 mhz changed fast_read maximum clock rate from 93 to 104 mhz changed dual i/o fast_read clock rate from 72 to 80 mhz and effective data rate from18 to 20 mb/s ordering information changed description for speed characters 0x from 93 to 104 mhz dc characteristics changed i li (input leakage current) value from 4 to 2 a (max) changed i lo (output leakage current) value from 4 to 2 a (max) changed i cc1 (active power supply current - read) test condition frequencies from 72/93/36 mhz to 80/104/40 mhz changed i cc1 (active power supply current - read) value @ 80 mhz (dual/quad) from 41.8 to 44 ma (max) changed i cc1 (active power supply current - read) value @ 104 mhz (serial) from 27.5 to 32 ma (max) changed i cc1 (active power supply current - read) value @ 40 mhz (serial) from13.2 to 15 ma (max) changed i cc2 (active power supply current - page program) value from 28.6 to 26 ma (max) changed i cc3 (active power supply current - wrr) value from 16.5 to 15 ma (max) changed i cc4 (active power supply current - se) value from 28.6 to 26 ma (max) changed i cc5 (active power supply current - be) value from 28.6 to 26 ma (max) added note 2, clarifying that bulk erase is on a die per die basis, not for the whole device test conditions added note clarifying that input rise and fall times are 0-100% ac characteristics changed f r (sck frequency for read/rdid) va lues from 36/45 to 40/50 mhz (max) changed f c (sck frequency for others) values from 93/72 to 104/80 mhz (max) changed t v (clock low to output valid) values from 9.6/11.4/7.8/9.6 to 9/10.5/7.8/9 ns (max) added t be (bulk erase time) added note 8 clarifying that bulk erase is on a die per die basis, not for the whole device added note 9 clarifying that a minimum time of t cs must be kept between the rising edge of one chip select and the falling edge of the other when switching between die for proper device functionality. capacitance merged c in capacitance values into a single line item merged single i/o, dual i/o, and quad i/o max capacitance values into a single line item added c in / c out (input / output capacitance) values of 6/8 pf (max) added notes clarifying test conditions revision 04 (june 24, 2011) global promoted data sheet designation from preliminary to full production
june 24, 2011 S70FL256P_00_04 S70FL256P 19 data sheet colophon the products described in this document are designed, developed and manufactured as contemplated for general use, including wit hout limitation, ordinary industrial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for any use that includes fatal risks or dangers that, unless extremely high safety is secured, could have a s erious effect to the public, and could lead directly to death, personal injury, severe physical damage or other loss (i.e., nuclear reaction control in nuclear facility, aircraft flight control, air traffic control, mass transport control, medical life support system, missile launch control in we apon system), or (2) for any use where chance of failure is intolerable (i.e., submersible repeater and artificial satellite). please note that spansion will not be liable to you and/or any third party for any claims or damages arising in connection with above-mentioned uses of the products. any semic onductor devices have an inherent chance of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restriction s on export under the foreign exchange and foreign trade law of japan, the us export administration regulations or the applicable laws of any oth er country, the prior authorization by the respective government entity will be required for export of those products. trademarks and notice the contents of this document are subject to change without notice. this document may contain information on a spansion product under development by spansion. spansion reserves the right to change or discontinue work on any product without notice. the informati on in this document is provided as is without warranty or guarantee of any kind as to its accuracy, completeness, operability, fitness for particular purpose, merchantability, non-infringement of third-party rights, or any ot her warranty, express, implied, or statutory. spansion assume s no liability for any damages of any kind arising out of the use of the information in this document. copyright ? 2010-2011 spansion inc. all rights reserved. spansion ? , the spansion logo, mirrorbit ? , mirrorbit ? eclipse?, ornand?, ecoram? and combinations thereof, are trademarks and registered tr ademarks of spansion llc in the united states and other count ries. other names used are for informational purposes only and may be trademarks of their respective owners.

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